Thesis can be developed either in Alameda or Taguspark campi. All thesis have the possibility of a research grant.
Interested? Drop me an email and we can talk about these (or other) topics.
Towards sustainable memory tiering operating systems
The emerging computer architectures comprise heterogeneous memory architectures, whose byte-addressable main memory includes not only DRAM but also other kinds of memory (such as persistent memory, high-bandwidth memory, memory expansion pools).
This revolution in computer architectures has required the operating system to implement memory tiering policies, in which the virtual memory layer decides at which memory tier each page should be placed.
While this recent hot topic has received much attention from a performance perspective, it is not well studied from an energy perspective.
The goal of this thesis is to study the energy usage trade-offs associated with the components that make up a memory tiering system (from access tracking and page classification to page migration) and, from such insights, understand how the page placement policies of state of the art systems can be changed to optimize energy usage.
To achieve this goal, the thesis will deploy and benchmark at least one memory tiering system, in real systems with heterogeneous memory architectures.
Some state of the art solutions for memory tiering:
https://dl.acm.org/doi/10.1145/3600006.3613167
https://dl.acm.org/doi/10.1145/3582016.3582063
https://dl.acm.org/doi/10.1145/3477132.3483550
The power of an L4 cache in modern heterogenous memory architectures
The emerging computer architectures comprise heterogeneous memory architectures, whose byte-addressable main memory includes not only DRAM but also other kinds of memory, such as Intel Optane Persistent Memory.
In Optane-equipped systems, the user has the option to use the DRAM memory as an L4 cache of the contents in Optane.
While this feature is advantageous for many workloads, the caching and eviction costs of the L4 cache can actually slow down the performance of many applications.
This thesis has 2 main goals:
1) Using a real Optane-equipped system, to study behaviour and performance trade-offs of the L4 cache featured in these systems.
2) Based on the above findings, design a hybrid approach, the operating system decides which pages of an application will benefit from the L4 cache (and, thus, are accessed through the L4 cache), and which pages perform better if the L4 cache is bypassed.
This design will then be implemented in a real system and experimentally evaluated with realistic workloads. A research paper is expected to be submitted to an international scientific conference.
References:
https://lenovopress.lenovo.com/lp1528-analyzing-the-performance-of-optane-persistent-memory-200-memory-mode
https://dl.acm.org/doi/10.1145/3492321.3519556
https://dl.acm.org/doi/10.1145/3451342
Dynamic page-level memory tiering with object-level hints
The goal of this thesis is to study how a page-level memory tiering system such as [1] can take advantage of object-level placement hints, either provided by an expert programmer or by existing profiling-based placement tools [2,3,4]. This integration will enable the dynamic page placement policies to leverage such additional knowledge from the higher layers in order to refine its predictions and, consequently, employ more efficient policies.
This knowledge can include information about which pages contain small ephemeral data, thus should always be kept in DRAM; or popularity scores assigned by the object-level layer to page ranges, which should be used to guide the placement policy of the memory tiering system.
[1] https://arxiv.org/abs/2112.12685
[2] https://core.ac.uk/download/pdf/132529093.pdf
[3] https://dl.acm.org/doi/10.1145/3126908.3126923
[4] https://ieeexplore.ieee.org/document/9912666/
Persistent hardware transactional memory in Intel Sapphire Rapids CPUs
The new family of high-end server processors by Intel, Sapphire Rapids, now supports shared memory synchronization with hardware transactions (Intel TSX) with new advanced features that were not available in previous generations. Concretely, there are new instructions that allow the program running inside a hardware transaction to suspend (and later resume) read tracking in the transaction.
Furthermore, the decision to discontinue Intel Optane Persistent Memory means that the new systems must resort back to fase PCIe-based SSD storage to maintain their persistent data structures.
The main goal of this thesis is to depart from SPHT [1], the state-of-the-art solution for persistent memory transactions relying on the previous version of Intel TSX, and redesign it to take into account the two above-mentioned trends (the opportunity of the new transactional instructions, and the restriction of no longer relying on byte-addressible persistent memory).
[1] https://www.usenix.org/conference/fast21/presentation/castro
[2] https://hmem-workshop.github.io/hmem-sc23/slides-papers/barreto-hmem-workshop-sc23.pdf